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NB100LVEP56 2.5V / 3.3V / 5V ECL Dual Differential 2:1 Multiplexer
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both individual and common select inputs to address both data path and random logic applications. Common and individual selects can accept both ECL and CMOS input voltage levels. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input operation, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
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20 1
20 N100 VP56 ALYW 1 24 1
24 1
TSSOP-20 DT SUFFIX CASE 948E
* Maximum Input Clock Frequency > 2.5 GHz Typical * Maximum Input Data Rate > 2.5 Gb/s Typical * 525 ps Typical Propagation Delays * Low Profile QFN Package * PECL Mode Operating Range: * NECL Mode Operating Range:
QFN-24 MN SUFFIX CASE 485L A L Y W
N100 VP56 ALYW
VCC = 2.375 V to 5.5 V with VEE = 0 V VCC = 0 V with VEE = -2.375 V to -5.5 V (Compatible with ECL and CMOS Input Voltage Levels)
* Separate, Common Select, and Individual Select
= Assembly Location = Wafer Lot = Year = Work Week
* Q Output Will Default LOW with Inputs Open or at VEE * Multiple VBB Outputs * Pb-Free Packages are Available*
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2004
December, 2004 - Rev. 5
1
Publication Order Number: NB100LVEP56/D
NB100LVEP56
Table 1. PIN FUNCTION DESCRIPTION
AAAAAAAA A AAAAAAAA A
TSSOP 14,20 11 QFN 3,9,18,19, 20 15,24 6,12 4 5 7 8 10 11 13 14 2 1 17 16 23 22 21 - 3,8 1 2 4 5 6 7 9 10 19 18 13 12 17 16 15 N/A
Pin No.
Name VCC VEE
I/O - - - ECL Input ECL Input ECL Input ECL Input ECL Input ECL Input ECL Input ECL Input ECL Output ECL Output ECL Output ECL Output ECL, CMOS Input ECL, CMOS Input ECL, CMOS Input -
Default State - - - Low High Low High Low High Low High - - - - Low Low Low
Description Positive Supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. ECL Reference Voltage Output Noninverted Differential Data a Input to MUX 0. Internal 75 kW to VEE. Inverted Differential Data a Input to MUX 0. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Data b Input to MUX 0. Internal 75 kW to VEE. Inverted Differential Data b Input to MUX 0. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Data a Input to MUX 1. Internal 75 kW to VEE. Inverted Differential Data a Input to MUX 1. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Data b Input to MUX 1. Internal 75 kW to VEE. Inverted Differential Data b Input to MUX 1. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Output MUX 0. Typically Terminated with 50 W to VTT = VCC - 2.0 V. Inverted Differential Output MUX 0. Typically Terminated with 50 W to VTT = VCC - 2.0 V. Noninverted Differential Output MUX 1. Typically Terminated with 50 W to VTT = VCC - 2.0 V. Inverted Differential Output MUX 1. Typically Terminated with 50 W to VTT = VCC - 2.0 V. Noninverted Differential Select Input to MUX 0. Internal 75 W to VEE. Noninverted Differential Common Select Input to Both MUX. Internal 75 W to VEE. Noninverted Differential Select Input to MUX 1. Internal 75 W to VEE. Exposed Pad. (Note 1)
VBB0, VBB1 D0a D0a D0b D0b D1a D1a D1b D1b Q0 Q0 Q1 Q1 SEL0 COM_SEL SEL1 EP
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit.
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D0a R1 D0a R1 D0b R1 D0b R1 D1a R1 D1a R1 D1b R1 D1b R1
R2
1
Q0 Q0
R2
R2
1
R2
Figure 1. Logic Diagram
COM_SEL
SEL0
SEL1
VCC
VCC
VEE
Q0
Q0
Q1
Q1
20
19
18
17
16
15
NB100LVEP56
1 D0a
2 D0a
3 VBBO
4 D0b
5 D0b
6 D1a
D1b
VBB1
D1a
D1b
Figure 2. TSSOP-20 Lead Pinout (Top View)
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection (R1) (R2) Human Body Model Machine Model Charged Device Model Value 75 kW 37 kW > 2 kV > 150 V > 2 kV Level 1 UL 94 V-0 @ 0.125 in 354 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
0 SEL0 R1 COM_SEL R1 SEL1 R1 Q1 Q1 0 VCC VEE 14 13 12 11 7 8 9 10 3
Table 2. TRUTH TABLE
SEL0 X L L H H SEL1 X L H H L COM_SEL H L L L L Q0, Q0 a b b a a Q1, Q1 a b a a b
COM VEE SEL0 SEL SEL1 VCC VCC 24 Q0 Q0 VCC D0a D0a VBB0 1 2 3 4 5 6 7 8 9 10 11 12 NB100LVEP56 23 22 21 20 19
Exposed Pad (EP)
18 17 16 15 14 13
VCC Q1 Q1 VEE D1b D1b
D0b D0b VCC D1a D1a VBB1
Figure 3. QFN-24 Lead Pinout (Top View)
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NB100LVEP56
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJA Parameter Positive Mode Power Supply Negative Mode Power Supply Positive Mode Input Voltage Negative Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) JEDEC 51-3 (1S - Single Layer Test Board) Thermal Resistance (Junction-to-Ambient) JEDEC 51-6 (2S2P-Multi Layer Test Board) with Filled Thermal Vias Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C <2 to 3 sec @ 260C TSSOP-20 TSSOP-20 QFN-24 QFN-24 TSSOP-20 QFN-24 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 "0.5 -40 to +85 -65 to +150 140 50 37 32 23 to 41 11 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C
qJC Tsol
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
Table 5. DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (SEL0, SEL1, COM_SEL) Input HIGH Voltage (D Inputs) (Note 4) Input LOW Voltage (SEL0, SEL1, COM_SEL) Input LOW Voltage (D Inputs) (Note 4) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) Input HIGH Current (@VIH) Input LOW Current (@VIL) D D SEL 0.5 -150 -150 Min 35 1355 555 1335 1335 VEE 555 1.2 Typ 45 1480 775 Max 55 1605 900 VCC 1620 875 875 2.5 150 0.5 -150 -150 Min 35 1355 555 1335 1335 VEE 555 1.2 25C Typ 45 1480 775 Max 55 1605 900 VCC 1620 875 875 2.5 150 0.5 -150 -150 Min 35 1355 555 1275 1275 VEE 555 1.2 85C Typ 48 1480 775 Max 58 1605 900 VCC 1620 875 875 2.5 150 Unit mA mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V. 3. All loading with 50 W to VCC - 2.0 V. 4. Do not use VBB at VCC < 3.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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Table 6. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (SEL0, SEL1, COM_SEL) Input HIGH Voltage (D Inputs) Input LOW Voltage (SEL0, SEL1, COM_SEL) Input LOW Voltage (D Inputs) Output Reference Voltage (Note 8) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) Input HIGH Current (@VIH) Input LOW Current (@VIL) D D SEL 0.5 -150 -150 Min 35 2155 1355 2135 2135 VEE 1355 1775 1.2 1875 Typ 45 2280 1575 Max 55 2405 1700 VCC 2420 1675 1675 1975 3.3 150 0.5 -150 -150 Min 35 2155 1355 2135 2135 VEE 1355 1775 1.2 1875 25C Typ 45 2280 1575 Max 55 2405 1700 VCC 2420 1675 1675 1975 3.3 150 0.5 -150 -150 Min 35 2155 1355 2135 2135 VEE 1355 1775 1.2 1875 85C Typ 48 2280 1575 Max 58 2405 1700 VCC 2420 1675 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V. 7. All loading with 50 W to VCC - 2.0 V. 8. Single-Ended input operation is limited to VCC w 3.0 V in PECL mode. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 7. DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 10)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 11) Output LOW Voltage (Note 11) Input HIGH Voltage (SEL0, SEL1, COM_SEL) Input HIGH Voltage (D Inputs) Input LOW Voltage (SEL0, SEL1, COM_SEL) Input LOW Voltage (D Inputs) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) Input HIGH Current (@VIH) Input LOW Current (@VIL) D D SEL 0.5 -150 -150 Min 40 3855 3055 3775 3775 VEE 3055 3475 1.2 3575 Typ 50 3980 3275 Max 60 4105 3400 VCC 4120 3375 3375 3675 5.0 150 0.5 -150 -150 Min 40 3855 3055 3775 3775 VEE 3055 3475 1.2 3575 25C Typ 50 3980 3275 Max 60 4105 3400 VCC 4120 3375 3375 3675 5.0 150 0.5 -150 -150 Min 45 3855 3055 3775 3775 VEE 3055 3475 1.2 3575 85C Typ 55 3980 3275 Max 65 4105 3400 VCC 4120 3375 3375 3675 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 11. All loading with 50 W to VCC - 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP56
Table 8. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -2.375 V (Note 13)
-40C Symbol IEE VOH VOL VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 14) Output LOW Voltage (Note 14) Input HIGH Voltage (SEL0, SEL1, COM_SEL) Input HIGH Voltage (D Inputs) Input LOW Voltage (SEL0, SEL1, COM_SEL) Input LOW Voltage (D Inputs) Output Reference Voltage (Note 15) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 16) Input HIGH Current (@VIH) Input LOW Current (@VIL) D D SEL 0.5 -150 -150 Min 35 -1145 -1945 -1165 -1165 VEE -1945 -1525 -1425 Typ 45 -1020 -1725 Max 55 -895 -1600 VCC -880 -1600 -1600 -1325 0.0 Min 35 -1145 -1945 -1165 -1165 VEE -1945 -1525 -1425 25C Typ 45 -1020 -1725 Max 55 -895 -1600 VCC -880 -1600 -1600 -1325 0.0 Min 35 -1145 -1945 -1165 -1165 VEE -1945 -1525 -1425 85C Typ 48 -1020 -1725 Max 58 -895 -1600 VCC -880 -1600 -1600 -1325 0.0 Unit mA mV mV mV
VIL
mV
VBB VIHCMR
mV V
VEE+1.2
VEE+1.2
VEE+1.2
IIH IIL
150 0.5 -150 -150
150 0.5 -150 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Input and output parameters vary 1:1 with VCC. 14. All loading with 50 W to VCC - 2.0 V. 15. Single-Ended input operation is limited to VEE from -3.0 V to -5.5 V in NECL mode. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 9. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -5.5 V (Note 17)
-40C Symbol IEE VOH VOL VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 18) Output LOW Voltage (Note 18) Input HIGH Voltage (SEL0, SEL1, COM_SEL) Input HIGH Voltage (D Inputs) Input LOW Voltage (SEL0, SEL1, COM_SEL) Input LOW Voltage (D Inputs) Output Reference Voltage (Note 19) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 20) Input HIGH Current (@VIH) Input LOW Current (@VIL) D D SEL 0.5 -150 -150 Min 40 -1145 -1945 -1165 -1165 VEE -1945 -1525 -1425 Typ 50 -1020 -1725 Max 60 -895 -1600 VCC -880 -1600 -1625 -1325 0.0 Min 40 -1145 -1945 -1165 -1165 VEE -1945 -1525 -1425 25C Typ 50 -1020 -1725 Max 60 -895 -1600 VCC -880 -1600 -1625 -1325 0.0 Min 45 -1145 -1945 -1165 -1165 VEE -1945 -1525 -1425 85C Typ 55 -1020 -1725 Max 65 -895 -1600 VCC -880 -1600 -1625 -1325 0.0 Unit mA mV mV mV
VIL
mV
VBB VIHCMR
mV V
VEE+1.2
VEE+1.2
VEE+1.2
IIH IIL
150 0.5 -150 -150
150 0.5 -150 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC - 2.0 V. 19. Single-Ended input operation is limited to VEE from -3.0 V to -5.5 V in NECL mode. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 V to -3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 21)
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (See Figure 4) Propagation Delay to Output Differential fin v 1 GHz fin = 2 GHz fin = 2.5 GHz D to Q, Q SEL to Q, Q COM_SEL to Q, Q Min 525 500 400 375 575 550 Typ 700 600 500 500 775 750 10 5 15 50 fin = 2.5 GHz fin =1.5 Gb/s fin = 2.5 Gb/s 150 Q, Q 5 15 800 1200 150 625 975 950 50 30 50 200 1 10 25 800 1200 150 Max Min 550 500 350 400 625 600 25C Typ 700 600 450 525 825 800 10 5 15 50 1 10 25 800 1200 mV ps 650 1025 1000 Max Min 500 400 200 450 700 700 85C Typ 700 500 300 575 900 900 10 5 15 50 700 1100 1100 50 30 50 200 1 Max Unit mV
tPLH, tPHL
ps
tSkew
Pulse Skew (Note 22) Within Device Input Skew (Note 23) Within Device Output Skew (Note 24) Device-to-Device Skew (Note 25) RMS Random Clock Jitter (Note 26) Peak-to-Peak Data Dependent Jitter (Note 27)
ps
tJITTER
ps
VINPP tr tf
Input Voltage Swing (Differential Configuration) (Note 28) Output Rise/Fall Times @ 50 MHz (20% - 80%)
60
110
150
60
120
170
90
140
230
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. Input edge rates 150 ps (20% - 80%). 22. Pulse Skew |tPLH - tPHL| 23. Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input. 24. Worst case difference between Q0 and Q1 outputs. 25. Skew is measured between outputs under identical transitions. 26. Additive RMS jitter with 50% Duty Cycle Clock Signal at fin = 2.5 GHz. 27. Additive Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at fin = 2.5 Gb/s. 28. Input voltage swing is a single-ended measurement operating in differential mode.
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Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = -4.2 V to -5.5 V or VCC = 4.2 V to 5.5 V; VEE = 0 V (Note 29)
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (See Figure 5) Propagation Delay to Output Differential fin v 1 GHz fin = 2 GHz fin = 2.5 GHz D to Q, Q SEL to Q, Q COM_SEL to Q, Q Min 600 550 400 375 575 550 Typ 750 650 550 500 775 750 5 15 20 50 fin = 2.5 GHz fin =1.5 Gb/s fin = 2.5 Gb/s 150 Q, Q 5 15 800 1200 150 625 975 950 50 30 50 200 1 10 25 800 1200 150 Max Min 600 500 350 400 625 600 25C Typ 750 600 450 525 825 800 5 15 20 50 650 1025 1000 50 30 50 200 1 10 20 800 1200 mV ps Max Min 600 400 200 450 700 700 85C Typ 750 500 300 575 900 900 5 15 20 50 700 1100 1100 50 30 50 200 1 Max Unit mV
tPLH, tPHL
ps
tSkew
Pulse Skew (Note 30) Within Device Input Skew (Note 31) Within Device Output Skew (Note 32) Device-to-Device Skew (Note 33) RMS Random Clock Jitter (Note 34) Peak-to-Peak Data Dependent Jitter (Note 35)
ps
tJITTER
ps
VINPP tr tf
Input Voltage Swing (Differential Configuration) (Note 36) Output Rise/Fall Times @ 50 MHz (20% - 80%)
60
110
150
60
120
170
90
140
230
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 29. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. Input edge rates 150 ps (20% - 80%). 30. Pulse Skew |tPLH - tPHL| 31. Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input. 32. Worst case difference between Q0 and Q1 outputs. 33. Skew is measured between outputs under identical transitions. 34. Additive RMS jitter with 50% Duty Cycle Clock Signal at fin = 2.5 GHz. 35. Additive Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at fin = 2.5 Gb/s. 36. Input voltage swing is a single-ended measurement operating in differential mode.
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850 OUTPUT VOLTAGE AMPLITUDE (mV) 750 650 550 450 350 JITTER (ps) 250 0.5 1.0 1.5 2.0 2.5 Q AMP (mV) 10.0 9.0 8.0 RMS JITTER (ps) 10.0 Q AMP (mV) 9.0 8.0 RMS JITTER (ps) 7.0 6.0 550 450 350 JITTER (ps) 250 0.5 1.0 1.5 INPUT FREQUENCY (GHz) 2.0 2.5 5.0 4.0 3.0 2.0 1.0 0.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 2.5 V, 255C
850 OUTPUT VOLTAGE AMPLITUDE (mV) 750 650
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 5.0 V, 255C
D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 6. AC Reference Measurement
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Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device NB100LVEP56DT* NB100LVEP56DTR2* NB100LVEP56MN NB100LVEP56MNG NB100LVEP56MNR2 NB100LVEP56MNR2G Package TSSOP-20 (Pb-Free) TSSOP-20 (Pb-Free) QFN-24 QFN-24 (Pb-Free) QFN-24 QFN-24 (Pb-Free) Shipping 75 Units / Rail 2500 Tape & Reel 92 Units / Rail 92 Units / Rail 3000 Tape & Reel 3000 Tape & Reel
*These devices are manufactured with a Pb-Free external lead finish only. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
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Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NB100LVEP56
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
L
B
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
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IIII IIII IIII
M DETAIL E DETAIL E
K K1
SECTION N-N 0.25 (0.010)
-W-
DIM A B C D F G H J J1 K K1 L M
NB100LVEP56
PACKAGE DIMENSIONS
QFN 24 MN SUFFIX 24 PIN QFN, 4x4 CASE 485L-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.35 0.45
D
PIN 1 IDENTIFICATION
A
B
E
2X
0.15 C
2X
0.15 C A2 0.10 C A
0.08 C
SEATING PLANE
A1 D2 e
12 13
A3
DIM A A1 A2 A3 b D D2 E E2 e L
REF
C
L
7 6
E2
24X
b
1 24 19
18
0.10 C A B 0.05 C
e
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13
NB100LVEP56
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NB100LVEP56/D

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